Título

Karatsuba-Ofman Multiplier with Integrated Modular Reduction for (2m )

Autor

Eduardo Cuevas Farfán

MIGUEL MORALES SANDOVAL

ALICIA MORALES REYES

CLAUDIA FEREGRINO URIBE

Ignacio Algredo Badillo

Paris Kitsos

RENE ARMANDO CUMPLIDO PARRA

Nivel de Acceso

Acceso Abierto

Resumen o descripción

In this paper a novel GF(2m) multiplier based on Karatsuba-Ofman Algorithm is presented. A binary field multiplication in polynomial basis is typically viewed as a two steps process, a polynomial multiplication followed by a modular reduction step. This research proposes a modification to the original Karatsuba-Ofman Algorithm in order to integrate the modular reduction inside the polynomial multiplication step. Modular reduction is achieved by using parallel linear feedback registers. The new algorithm is described in detail and results from a hardware implementation on FPGA technology are discussed. The hardware architecture is described in VHDL and synthesized for a Virtex-6 device. Although the proposed field multiplier can be implemented for arbitrary finite fields, the targeted finite fields are recommended for Elliptic Curve Cryptography. Comparing other KOA multipliers, our proposed multiplier uses 36% less area resources and improves the maximum delay in 10%.

Editor

Advances in Electrical and Computer Engineering

Fecha de publicación

2013

Tipo de publicación

Artículo

Versión de la publicación

Versión aceptada

Formato

application/pdf

Idioma

Inglés

Audiencia

Estudiantes

Maestros

Público en general

Sugerencia de citación

Cuevas, E., et al., (2013). Karatsuba-Ofman Multiplier with Integrated Modular Reduction for GF(2m), Advances in Electrical and Computer Engineering, Vol. 13 (2): 3-10

Repositorio Orígen

Repositorio Institucional del INAOE

Descargas

189

Comentarios



Necesitas iniciar sesión o registrarte para comentar.