Título
On an external memory scheme for processor arrays
Autor
JOSE ROBERTO PEREZ ANDRADE
CESAR TORRES HUITZIL
RENE ARMANDO CUMPLIDO PARRA
Nivel de Acceso
Acceso Abierto
Materias
Prosessor arrays - (PROSESSOR ARRAYS) Loop-based Algorithms - (LOOP-BASED ALGORITHMS) External Memory Interface - (EXTERNAL MEMORY INTERFACE) FPGA - (FPGA) CIENCIAS FÍSICO MATEMÁTICAS Y CIENCIAS DE LA TIERRA - (CTI) MATEMÁTICAS - (CTI) CIENCIA DE LOS ORDENADORES - (CTI) CIENCIA DE LOS ORDENADORES - (CTI)
Resumen o descripción
The problem of generating memory interfaces between loop-based accelerators and external memory is gaining the attention from the high-level synthesis research community. This paper presents an external memory system for inserting/extracting data to/from a loop-based accelerator derived by a high-level synthesis approach. The memory system is composed by four architectural cases which could occur during hardware synthesis. The memory system is based on a global asynchronous local synchronous approach and the use of dualport memory banks. FPGA-based implementation results show that the proposed memory system is technologically achievable and provides a high-bandwidth without introducing communication overhead.
Editor
Electronics Express
Fecha de publicación
2013
Tipo de publicación
Artículo
Versión de la publicación
Versión aceptada
Recurso de información
Formato
application/pdf
Idioma
Inglés
Audiencia
Estudiantes
Investigadores
Público en general
Sugerencia de citación
Perez-Andrade, R., et al., (2013). On an external memory scheme for processor arrays, Vol. 10 (14): 1-12
Repositorio Orígen
Repositorio Institucional del INAOE
Descargas
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